Static Random Access Memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. Typically, in the formation of the SRAM, a plurality of SRAM cells is arranged as an array having a plurality of rows and a plurality of columns. An SRAM array typically has millions of SRAM cells. Due to the large number of SRAM cells in the SRAM cell array, reducing the layout size of the SRAM cells is critical for increasing the number of SRAM cells in a large SRAM array. To reduce the size of SRAM cells, the sizes of P-type Metal-Oxide-Semiconductor (PMOS) transistors and N-type Metal-Oxide-Semiconductor (NMOS) transistors in the SRAM cells are reduced. Furthermore, the distance between neighboring PMOS devices and NMOS devices are also reduced.